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A heteroassociative memory using current-mode MOS analog VLSI circuits

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4 Author(s)
Boahen, K.A. ; Johns Hopkins Univ., Baltimore, MD, USA ; Pouliquen, P.O. ; Andreou, A.G. ; Jenkins, R.E.

A description is given of a scalable architecture for the implementation of neural networks that produces regular and dense designs. A combination of low power consumption and enhanced performance is achieved by using analog current-mode MOS circuits operating in subthreshold conduction. The authors have designed and fabricated a bidirectional associative memory in 3-μm bulk CMOS. The chip has 46 neurons arranged in three layers, namely, a hidden layer and two input/output layers. There are 448 repeatedly programmable connections. This chip performs two-way associative search for stored vector pairs and has optimal storage efficiency of one hardware bit per information bit. The synaptic elements have bipolar current outputs. These currents are integrated using the interconnect capacitance to determine the activation of the thresholding neurons. The unit synaptic current I u is externally programmable. Recall rates of 100000 vectors per second have been obtained with Iu=0.5 μA

Published in:

Circuits and Systems, IEEE Transactions on  (Volume:36 ,  Issue: 5 )

Date of Publication:

May 1989

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