By Topic

A digital architecture employing stochasticism for the simulation of Hopfield neural nets

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
D. E. Van Den Bout ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; T. K. Miller

A digital architecture which uses stochastic logic for simulating the behavior of Hopfield neural networks is described. This stochastic architecture provides massive parallelism (since stochastic logic is very space-efficient), reprogrammability (since synaptic weights are stored in digital shift registers), large dynamic range (by using either fixed- or floating-point weights), annealing (by coupling variable neuron gains with noise from stochastic arithmetic), high execution speed (≈N×108 connections per second), expandability (by cascading of multiple chips to host large networks), and practicality (by building with very conservative MOS device technologies). Results of simulations are given which show the stochastic architecture gives results similar to those found using standard analog neural networks or simulated annealing

Published in:

IEEE Transactions on Circuits and Systems  (Volume:36 ,  Issue: 5 )