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TRIM: testability range by ignoring the memory

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3 Author(s)
Carter, L. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Huisman, L.M. ; Williams, T.W.

The testability by random test patterns of faults in the logic surrounding embedded RAMs is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 1 )