By Topic

The design of concurrent error diagnosable systolic arrays for band matrix multiplications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chan, S.-W. ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA ; Chin-Long Wey

The characteristics of a systolic array and the important issues in fault-tolerant systolic computing are presented. Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of systolic design in order to exemplify the extremes in design philosophies. The motivations for additional figures of merit are pointed out, and a novel BMMSA design is introduced. An efficient scheme, based on the time-redundancy technique of RESO (recomputation with shifted operands), is applied to the design of CED-capable BMMSAs. Different designs, based on the Kung-Leiserson BMMSA, the proposed BMMSA, and the Huang-Abraham BMMSA, are presented

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 1 )