On the role of hardware reset in synchronous sequential circuit test generation

The existence of hardware reset facilitates the test generation process for synchronous sequential circuits, as compared to test generation that starts from an unspecified initial state. Conventionally, therefore, when hardware reset is available, it is used to reset all state variables to predetermined values, conventionally 0, before a test sequence is applied. In this paper, we show that full hardware reset (i.e., reset that sets all state variables to 0) may sometimes result in test lengths and numbers of undetectable faults which are higher than the corresponding results when partial reset is used, i.e., when only a subset of the state variables are resettable, while the others retain their previous values (unspecified when the circuit is first operated) when reset is applied. The main advantage of partial reset over full reset is that while full reset is only useful once, at the beginning of a test sequence, partial reset can be used while the test sequence is being applied, to transfer the machine from one state to another. Experimental results are provided to support the use of partial reset, a procedure for selecting the state variables for partial reset is developed, and a test generation procedure valid under partial reset is presented