Referenced Items are not available for this document.
The authors present a new technology mapping algorithm for an LUT-based FPGA. Decomposition of a Boolean network is formulated as an algebraic cofactoring, and the technology mapping is performed by cofactor packing. Experimental results show that the proposed method decomposes infeasible nodes in a shorter CPU time with more than 10% reduced number of nodes compared with previous decomposition methods
Published in:
Electronics Letters
(Volume:30
,
Issue:
15
)
Date of Publication: 21 Jul 1994
- Page(s):
- 1207 - 1209
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 4760997
- Digital Object Identifier :
- 10.1049/el:19940862
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 21 Jul 1994
- Sponsored by :
- Institution of Engineering and Technology
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
