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An all digital receiver architecture for bandwidth efficient transmission at high data rates

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4 Author(s)
Ascheid, G. ; Aachen Univ. of Technol., West Germany ; Oerder, M. ; Stahl, J. ; Meyr, H.

Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions

Published in:

Communications, IEEE Transactions on  (Volume:37 ,  Issue: 8 )

Date of Publication:

Aug 1989

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