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1-Mb memory chip using giant magnetoresistive memory cells

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2 Author(s)
Brown, J.L. ; Nonvolatile Electronics Inc., Eden Prairie, MN, USA ; Pohm, A.V.

A 1-Mb nonvolatile, nondestructive readout M-R memory chip using elements with Giant Magnetoresistance Ratio (GMR) material has been designed. The chip employs dual redundancy, CMOS drive electronics with minimum gate lengths of 0.8 microns, two metal layers, and a 5-V ±10% power supply. The layout has an area of 0.9 cm sq, and approximately 50% of the chip area is devoted to the memory cell array. The memory chip is designed around 1.4 μm×6.1 μm, 80-Ω elements using GMR material; the elements are spaced 1.4 μm apart. The material is composed of two 50-Å ternary alloy layers separated by 30 Å of copper and has a nominal M-R coefficient of 6.0%. Minimum read signal is ±2.5 mV; sense current is 2.5 mA; work current is ±30 mA; and input and output is 4b wide. The memory employs a new read scheme in which two-phase sensing is employed. The scheme provides a sensitive, stable output and diminishes the array area by a factor of two, at the expense of read access time. The design contains over 700000 transistors and over 2 million memory cells; a prototype 64 K section of this design has been built, but the full design has yet to be constructed on silicon. The design demonstrates that with GMR memory cells, M-R memories can be designed with densities and speeds comparable to dynamic RAM's

Published in:

Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on  (Volume:17 ,  Issue: 3 )