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Loop based design for wafer scale systems

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2 Author(s)
Pelletier, R.V. ; Bell-Northern Res., Ottawa, Ont., Canada ; McLeod, R.D.

This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:2 ,  Issue: 3 )