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Certified timing verification and the transition delay of a logic circuit

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4 Author(s)
S. Devadas ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; K. Keutzer ; S. Malik ; A. Wang

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:2 ,  Issue: 3 )