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Design of a pipelined datapath synthesis system for digital signal processing

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2 Author(s)
Hong-Shin Jun ; Dept. of Electr. Eng., Sogang Univ., Seoul, South Korea ; Sun-Young Hwang

In this paper, we describe the design of SODAS-DSP (Sogang Design Automation System-DSP), a pipelined datapath synthesis system targeted for application-specific DSP chip design. Through facilitated user interaction, the design space of pipelined datapaths for given design descriptions can be explored to produce an optimal design which meets design constraints. Taking SFG (Signal Flow Graph) in schematic as inputs, SODAS-DSP generates pipelined datapaths through scheduling and module allocation processes. New scheduling and module allocation algorithms are proposed for efficient synthesis of pipelined hardwares. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equidistribution of operations among pipeline partitions is adopted as the objective function. Module allocation is performed in two passes: the first pass for initial allocation and the second one for seduction of interconnection cost. In the experiments, we compare the synthesis results for benchmark examples with those of recent pipelined datapath synthesis systems, Sehwa and PISYN, and show the effectiveness of SODAS-DSP.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:2 ,  Issue: 3 )