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A method for modeling the manufacturability of IC designs

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3 Author(s)
Boskin, E.D. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Spanos, Costas J. ; Korsh, G.J.

A methodology for modeling the manufacturability of MOS circuits has been developed. The fabrication line is described using a small set of measurable process parameters, whose variation explains the range of circuit performance seen during production. These same parameters form the basis of a statistical MOSFET model which combines physical measurements, global optimization, and regression modeling of key fitting parameters to accurately predict transistor characteristics over a wide range of process variation. The fabrication line description in conjunction with the MOSFET model was used to develop a manufacturing application, specifically, a performance prediction model which uses the process parameters as measured on the manufacturing floor to predict the performance of fabricated integrated circuits before packaging and final test. The MOSFET model and the performance prediction model are integrated, and data taken from the manufacturing line can be used to verify the models, to identify process shifts, and suggest design improvements for further manufacturability enhancements. The method was successfully applied to an industrial 1.5-μm CMOS process, and models were developed and tested for a 1-Mbit EPROM

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:7 ,  Issue: 3 )