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Modeling of real defect outlines and parameter extraction using a checkerboard test structure to localize defects

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2 Author(s)
C. Hess ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; A. P. Stroele

For efficient yield prediction and inductive fault analysis, it is usually assumed that defects have the shape of circular discs or squares. Real defects, however, exhibit a great variety of different shapes. This paper presents a more accurate model. The defect outline is approximated by an ellipse, and an equivalent circular defect is determined that causes a fault with the same probability as the real defect. To utilize this model, only the maximum and the minimum extension of detected defects have to be determined. That can be done easily using a novel test structure design. The checkerboard test structure uses the boundary pad frame of standard chips and thus achieves a large defect sensitive area. This area is partitioned into many small regions that can be analyzed separately. Defects are localized by simple electrical measurements. This allows an efficient optical inspection that can provide detailed information about the detected defects

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:7 ,  Issue: 3 )