By Topic

Capacitance calculation of IC packages using the finite element method and planes of symmetry

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tai-Yu Chou ; Adv. Package Dev. Group, LSI Logic Corp., Fremont, CA, USA ; Z. J. Cendes

Finite element techniques are presented for determining the capacitance of three-dimensional interconnection structures. Results are presented for two typical intergrated circuits packages: the plastic leaded chip carrier (PLCC) and the dual in-line package (DIP). The symmetry of the capacitance matrix in the package is described and a set of formulas is presented to take advantage of this symmetry in capacitance calculation. This leads to the reduction in CPU time and memory usage and better converged solution

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:13 ,  Issue: 9 )