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A multilevel optimization technique is developed for large-scale and hierarchical optimization of high-speed VLSI interconnects modeled by distributed transmission lines. Mathematical programming decomposition is combined with network tearing where the overall network is optimized by a set of parallel suboptimizations. The technique takes advantage of VLSI interconnects in the hierarchy of IC, multichip modules (MCM) and printed circuit board (PCB), and is faster than standard optimization. The convergence property of the technique is derived through Gauss-Seidel relaxation analysis and optimality conditions for the multiple suboptimizations
Published in:
Microwave Theory and Techniques, IEEE Transactions on
(Volume:42
,
Issue:
9
)
Date of Publication: Sep 1994
- Page(s):
- 1638 - 1650
- ISSN :
- 0018-9480
- INSPEC Accession Number:
- 4780843
- Digital Object Identifier :
- 10.1109/22.310557
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Sep 1994
- Sponsored by :
- IEEE Microwave Theory and Techniques Society
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