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Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction

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3 Author(s)
Rijnders, L. ; IMEC, Heverlee, Belgium ; Six, P. ; de Man, H.J.

A method to design cell libraries for macrocell layouts, which are constructed as an array of cells, is discussed. It is based on symbolic layout and a hierarchical compaction algorithm. This algorithm provides automatic terminal fitting and compacts cells in such a way that translated and mirrored cells are kept identical. The cells can be changed with a set of parameters by a macrocell generator. The compaction technique then guarantees that no design-rule errors occur for any combination of the parameter values. The method also allows easy adaptability to circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established its cells can be used over and over again with different personality matrices for fast generation of correct layout.<>

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 3 )

Date of Publication:

June 1988

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