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Energy control and accurate delay estimation in the design of CMOS buffers

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2 Author(s)
Sha Ma ; Sun Microsyst. Comput. Corp., Sunnyvale, CA, USA ; Franzon, P.

The purpose of this paper is to present a computer aided method to design CMOS multistage variable-taper buffers with optimum energy efficiencies while satisfying speed requirements. The resulting designs typically save at least 20-30% energy per computation over conventionally designed circuits with the same speed. We also present a technique for obtaining accurate empirical delay equations for buffers

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 9 )