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A 3-level asynchronous protocol for a differential two-wire communication link

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2 Author(s)
C. Svensson ; LSI Design Center, Linkoping Univ., Sweden ; Jiren Yuan

A differential two-wire communication link with a 3-level asynchronous protocol is introduced. The proposed 3-level code contains information of both data and clock. Since only one edge is needed for each bit, the bandwidth of a link is efficiently utilized. The power consumption is reduced by the low-swing differential two-wire link and is further reduced by a 3-level code. The speed of the protocol is expected to reach 1 Gb/s in a 1.2-μm CMOS process

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 9 )