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A CMOS time to digital converter IC with 2 level analog CAM

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7 Author(s)
Gerds, E.J. ; Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA ; Van der Spiegel, J. ; Van Berg, R. ; Williams, H.H.
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A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-μm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of <35 ps, and a typical integral nonlinearity of <200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~1 s range could be realized

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Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 9 )