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A BiCMOS process utilizing selective epitaxy for analog/digital applications

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3 Author(s)
K. K. O ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; H. -S. Lee ; R. Reif

A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an fT of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n+ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits

Published in:

IEEE Transactions on Electron Devices  (Volume:36 ,  Issue: 7 )