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On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

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1 Author(s)
Hosseini, S.H. ; Dept. of Electr. Eng. & Comput. Sci., Wisconsin Univ., Milwaukee, WI, USA

A study is made of the design of fault-tolerant array processors. It is shown how hardware redundancy can be used in the existing structures in order to make them capable of withstanding the failure of some of the array links and processors. Distributed fault-tolerance schemes are introduced for the diagnosis of the faulty elements, reconfiguration, and recovery of the array. Fault tolerance is maintained by the cooperation of processors in a decentralized form of control without the participation of any type of hardcore or fault-free central controller such as a host computer. Time redundancy is utilized by assigning the functions of the failed processors to fault-free processors

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Computers, IEEE Transactions on  (Volume:38 ,  Issue: 7 )