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A versatile, SOI BiCMOS technology with complementary lateral BJT's

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6 Author(s)
Parke, S. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Assaderaghi, F. ; Jian Chen ; King, J.
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A silicon-on-insulator, fully-complementary BiCMOS process has been developed for realizing high-performance circuit operation in the sub-3.3 V power supply regime. Complementary, double-diffused lateral BJTs and fully-overlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film SOI substrates. The BJTs exhibit the highest lateral current gains reported to date, with h/sub fe/=120 and 225 for the NPN and PNP, respectively. NPN f/sub t/=4.5 GHz was achieved, and f/sub t/>20 GHz is possible with an improved layout. The MOSFETs demonstrate excellent short-channel behavior down to L/sub eff/=0.18 mu m, with T/sub ox/=10 nm. The p+ gate, SOI PMOS device exhibits superior I/sub dsat/ and g/sub msat/. A record propagation delay of 12 ps/stage at V/sub dd/=5 V and 300 K was obtained for the CMOS ring oscillators fabricated in this technology. This demonstrates the performance achievable with a deep-submicron SOI process.<>

Published in:

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Date of Conference:

13-16 Dec. 1992