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Digital circuit verification using partially-ordered state models

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2 Author(s)
Bryant, R.E. ; Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Seger, C.-J.H.

Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over “weakened” state values. This technique has long been practiced with logic simulators, using the value X to indicate a signal that could be either 0 or 1. This concept can be formally extended to a wider class of circuit models and signal values, yielding lattice-structured state domains. For more precise modeling of circuit operation, these values can be encoded in binary and hence represented symbolically as ordered binary decision diagrams. The net result is a tool for formal verification that can apply a hybrid of symbolic and partially-ordered evaluation

Published in:

Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on

Date of Conference:

25-27 May 1994