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Design of fault-tolerant cellular arrays on multiple-valued logic

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3 Author(s)
N. Kamiura ; Fac. of Eng., Himeji Inst. of Technol., Hyogo, Japan ; Y. Hata ; K. Yamato

This paper discusses the problems of the design and the fault tolerance in multiple-valued cellular arrays by considering the single-level array, the two-level array and the three-level array. These arrays are constructed by some cells that have the unique switch operation. It assumes the stuck-at-0 fault and the stuck-at-(k-1) fault of the switch cells on k-valued cellular arrays. The fault-tolerant arrays for the single fault are constructed by building a duplicate row and a duplicate column iteratively in the arrays. By evaluating three types for the design, the fault tolerance and the testability for multiple faults, it clarifies that the two-level array is the most suitable structure. Finally, the comparison with formerly presented arrays shows advantages for our fault-tolerant two-level array

Published in:

Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on

Date of Conference:

25-27 May 1994