By Topic

Scalable I/O architecture for buses

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
D. V. James ; Apple Comput., Cupertino, CA, USA

The author discusses current IEEE activities on the P1394 bus standard (1 Mb/s) and the P1596 interconnect (1 Gb/s), which concern the definition of standard control register locations, formats, and functions. This scalable definition, called an I/O architecture, is being considered for use by other bus standards as well (P896.1 Futurebus and the P1014 VME bus standards). The scalable I/O architecture definition is bus-technology-independent, and supports large multiple-bus configurations. Several of the scalable features of the I/O architecture are described.<>

Published in:

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Date of Conference:

Feb. 27 1989-March 3 1989