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A compact design for a highly-parallel shared-memory MIMD computer

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4 Author(s)
R. Kenner ; Courant Inst. of Math. Sci., New York Univ., NY, USA ; R. Bianchini ; S. Dickey ; P. J. Teller

The ultracomputer architecture connects hundreds or possibly thousands of processing elements (PEs), each containing a cache but no local memory, to an equal number of memory modules (MMs) via an interconnection network constructed of custom VLSI components that combine (merge) requests from different PEs destined to the same memory location. The network provides a high-bandwidth path from the PEs to MMs, but the memory latency is significantly larger than that encountered in either a uniprocessor or small bus-based multiprocessor. The PE must utilize the high available bandwidth and minimize the effect of network latency. The authors present a design of a 64-PE ultracomputer prototype using AMD AM29000 CPUs, including a description of system packaging using a backplane-free technology. The prototype is expected to be operational in 1990.<>

Published in:

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Date of Conference:

Feb. 27 1989-March 3 1989