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Shared memory multiprocessors: the right approach to parallel processing

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7 Author(s)
Woodbury, P. ; Encore Comput. Corp., Marlborough, MA, USA ; Wilson, A. ; Shein, B. ; Gertner, I.
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The authors discuss the inherent bandwidth limitations of shared buses, which are assumed to set a ceiling on the performance and scalability of this architecture. They report on three years of experience with production multiprocessor systems. Advances in bus and cache technologies have greatly raised the ceiling which limits the throughput of bus-based multiprocessors. Sophisticated hierarchies of buses and caches increase the range over which such systems may scale. Most importantly, the symmetrical shared-memory model continues to allow these systems to be programmed in a very general and straightforward way, a claim which is not common to any other multiprocessor architecture. It is shown that the shared-memory model makes development of parallel programs easier than with distributed memory machines.<>

Published in:

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Date of Conference:

Feb. 27 1989-March 3 1989