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Integration of CMOS-electronics in an SOI layer on high-resistivity silicon substrates

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20 Author(s)

The monolithic integration of electronics and high-resistivity silicon detectors is reported. The approach is based on CMOS circuit integration in the top layer of high-resistivity SOI (silicon-on-insulator) wafers. In a preliminary feasibility study, high-resistivity wafers were subjected to SOI layer fabrication methods and evaluated with a simple diode process for two main characteristics: diode leakage and possible dopant concentration increase. In the second phase of the project, a full SOI-on-HΩ process was executed. MOSFET behavior was then evaluated

Published in:

Nuclear Science Symposium and Medical Imaging Conference, 1992., Conference Record of the 1992 IEEE

Date of Conference:

25-31 Oct 1992

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