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A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog to digital converter integrated circuit

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2 Author(s)
Milgrome, O.B. ; Lawrence Berkeley Lab., California Univ., CA, USA ; Kleinfelder, S.A.

A monolithic CMOS 16-channel, 12 bit, 10-μs analog-to-digital converter has been designed and tested. The circuit converts 16 channels in parallel via a single slope ramp and Gray code counter algorithm. When biased for 10.0 μs conversions of a 2 V input range into 4050 voltage bins and ohmically connected to a computer, initial testing shows that typical performance is a noise level of 0.3 bins, rms, integral nonlinearity of 4 bins, adjacent channel crosstalk effects less than 1 bin, and total chip power consumption of 110 mW. The chip contains 16 sample and hold circuits, out of range logic, a Gray-to-binary converter, and tri-state data outputs for microprocessor compatibility. The die size is 4.4×1.5 mm in a 2 polysilicon, 1.2. μ feature size CMOS process, and has 52 bonding pads. Off-chip requirements are a single power supply, a single high-speed clock, a precision voltage reference, three biasing resistors, and supply filtering capacitors. This custom circuit has advantages of lower power dissipation and less PC board area than competitive approaches, and is designed for further monolithic system integration

Published in:

Nuclear Science Symposium and Medical Imaging Conference, 1992., Conference Record of the 1992 IEEE

Date of Conference:

25-31 Oct 1992