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VLSI implementation of a neural network model

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3 Author(s)
Graf, H.P. ; AT&T Bell Lab., Holmdel, NJ, USA ; Jackel, L.D. ; Hubbard, W.E.

The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network.<>

Published in:

Computer  (Volume:21 ,  Issue: 3 )

Date of Publication:

March 1988

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