By Topic

Performance analysis of an ATM switch capable of supporting multiclass traffic

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Seman, K. ; Dept. of Elect. & Electron. Eng., Strathclyde Univ., Glasgow, UK ; Smith, D.G.

The future ATM based B-ISDN is expected to accommodate multiclass traffic in which each class demands peculiar performance requirements in terms of delay and packet loss. In order to cope with such requirements, an ATM switch must be designed to provide low delay and low packet loss. This can be achieved by incorporating priority mechanisms in which priority for service is granted to the most delay-sensitive traffic, and priority to occupy buffer space is given to the most loss-sensitive traffic. The authors examine the performance of a multiplane switch architecture that is capable of supporting multiclass traffic. Performance measures such as mean delay and switch throughput for each class are presented

Published in:

Teletraffic Symposium, 10th. Performance Engineering in Telecommunications Network, Tenth UK

Date of Conference:

14-16 Apr 1993