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Parallel computation of neural networks in a processor pipeline with partially shared memory

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2 Author(s)
Okawa, Y. ; Osaka Univ., Japan ; Suyama, T.

A new parallel architecture of a processor pipeline is proposed. It is a linearly connected processor via dual bank switchable memory blocks. A layered neural network with the backpropagating error algorithm is adopted as a benchmark test. The essential part of the algorithm is multiplication of a matrix with a vector. A few additional data transfer operations are necessary. An experimental system is built, and several measurements are made. These prove the feasibility of the proposed architecture in some fields of practical application

Published in:

Neural Networks, 1993., IEEE International Conference on

Date of Conference:

1993