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Efficient FIR filter architectures suitable for FPGA implementation

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1 Author(s)
Evans, J.B. ; Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA

This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA)

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:41 ,  Issue: 7 )