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Area-time efficient modulo 2n-1 adder design

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3 Author(s)
Efstathiou, C. ; Dept. of Telematics, Hellenic Telecommun. Org. SA, Athens, Greece ; Nikolos, D. ; Kalamatianos, J.

In this paper the design of modulo 2n-1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with respect to speed and the cost function area-time product, than the corresponding adders already known from open literature

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:41 ,  Issue: 7 )