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Learning in linear systolic neural network engines: analysis and implementation

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3 Author(s)
Jones, S.R. ; Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK ; Sammut, K.M. ; Hunter, J.

Linear systolic processor arrays are a widely proposed digital architecture for neural networks. This paper reports the analysis of a range of training algorithms implemented on a linear systolic ring, with a view to (a) identifying low-level instruction requirements, (b) assessing different hardware structures for PE implementation and (c) evaluating the impact of different array controller designs. Quantitative data is derived and used to determine cost-effective PE and controller hardware constructs

Published in:

Neural Networks, IEEE Transactions on  (Volume:5 ,  Issue: 4 )

Date of Publication:

Jul 1994

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