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A space-efficient short-finding algorithm [VLSI layouts]

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3 Author(s)
Shun-Lin Su ; AT&T Bell Labs., Allentown, PA, USA ; Barry, C.H. ; Chi-Yuan Lo

A common method of locating electrical shorts in VLSI layouts is to build a connectivity graph of the shorted net and then find the shortest path between the two offending signals. The memory requirement of this method is proportional to the size of the net, which can be quite large. This paper presents a dynamic graph construction algorithm that significantly reduces the peak memory requirement. The algorithmic framework allows continuous trade-offs between run times and memory requirements

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:13 ,  Issue: 8 )

Date of Publication:

Aug 1994

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