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Velocity saturation in the extrinsic device: a fundamental limit in HFET's

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2 Author(s)
Greenberg, D.R. ; MIT, Cambridge, MA, USA ; del Alamo, J.A.

We have carried out an experimental study revealing that velocity saturation (υsat) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET's. Using AlGaAs/n+-InGaAs HFET's as a vehicle, we find that first gm and eventually fT decline at high currents in two stages. Initially, the approach of υsat in the extrinsic device causes the small-signal source and drain resistances (rs and rd) to rise dramatically, primarily degrading gm. As the current increases further, the large-signal source and drain resistances (Rs and Rd) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of rs and rd, the accompanying increase in gate-drain capacitance forces fT to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime

Published in:

Electron Devices, IEEE Transactions on  (Volume:41 ,  Issue: 8 )

Date of Publication:

Aug 1994

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