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7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's

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8 Author(s)
Zhi-Gong Wang ; Fraunhofer-Inst. fur Angewandte Festkorperphys., Freiburg, Germany ; Berroth, M. ; Nowotny, U. ; Hofmann, P.
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A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V

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Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 8 )