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Precise analog synapse for Kohonen feature maps

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2 Author(s)
P. Heim ; Lab. d'Electron. Gen., Ecole Polytech. Federale de Lausanne, Switzerland ; E. A. Vittoz

A plastic medium-term analog synapse is presented that fulfils the stringent specifications necessary for the Kohonen algorithm. The principle is based on a switched capacitor-like technique implementing a variable time-constant integrator. The memory leakage standard deviation is 2 mV/s for a voltage range of 2 V at room temperature and the learning gain can be varied over two decades. Its differential structure leads to good CMRR, PSRR, and charge injection cancellation. The total synapse area is &frac116; mm2 using a 3-μm self-aligned contact single-metal CMOS technology. Measurement results of a test chip are also presented

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 8 )