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Physical scaling and interconnection delays in multichip modules

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1 Author(s)
Frye, R.C. ; AT&T Bell Labs., Murray Hill, NJ, USA

This papers analyzes the ways that physical scaling of electrical interconnecting structures impacts their delays, with particular focus on multichip modules. We use for illustration example structures typical of laminate and thin-film based MCMs. Because multichip modules have higher packaging densities than conventional packaging, loading plays a correspondingly more important role in their delays. The most important parameters dominating the performance of MCMs are the average distance between the chips (i.e. the packaging density), the size of the load capacitance and the number of loads connected to the line. Focusing attention on these areas has the greatest potential to improve MCM performance, regardless of the particular substrate technology

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:17 ,  Issue: 1 )

Date of Publication:

Feb 1994

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