By Topic

Physical scaling and interconnection delays in multichip modules

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Frye, R.C. ; AT&T Bell Labs., Murray Hill, NJ, USA

This papers analyzes the ways that physical scaling of electrical interconnecting structures impacts their delays, with particular focus on multichip modules. We use for illustration example structures typical of laminate and thin-film based MCMs. Because multichip modules have higher packaging densities than conventional packaging, loading plays a correspondingly more important role in their delays. The most important parameters dominating the performance of MCMs are the average distance between the chips (i.e. the packaging density), the size of the load capacitance and the number of loads connected to the line. Focusing attention on these areas has the greatest potential to improve MCM performance, regardless of the particular substrate technology

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:17 ,  Issue: 1 )