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Specification and validation of control-intensive IC's in hopCP

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2 Author(s)
V. Akella ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; G. Gopalakrishnan

Control-intensive IC's pose a significant challenge to the users of formal methods in designing hardware. These IC's have to support a wide variety of requirements including synchronous and asynchronous operations, polling and interrupt driven modes of operation, multiple concurrent threads of execution, nontrivial computational requirements, and programmability. We illustrate the use of formal methods in the design of a control-intensive IC called the “Intel 8251” Universal Synchronous/Asynchronous Receiver/Transmitter (USART), using our hardware description language “hopCP”. A feature of hopCP is that it supports communication via asynchronous ports in addition to synchronous message passing. Asynchronous ports are distributed shared variables writable by exactly one process. We show the usefulness of this combination of communication constructs. We outline algorithms to determine safe usages of asynchronous ports, and also to discover other static properties of the specification. We discuss a compiled-code concurrent functional simulator called CFSIM, as well as the use of concurrent testers for driving CFSIM. The use of a semantically well-specified and simple language, and the associated analysis/simulation tools helps conquer the complexity of specifying and validating control-intensive IC's

Published in:

IEEE Transactions on Software Engineering  (Volume:20 ,  Issue: 6 )