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Low-voltage, four-quadrant, analogue CMOS multiplier

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1 Author(s)

A CMOS four quadrant analogue multiplier that can operate from a supply voltage of 1.5 V is described. The multiplier requires two linear transconductors whose input transistors are operated in their linear region. Simulation results indicate that the nonlinearity can be kept below 0.8%, across the entire differential input voltage range of ±400 mV

Published in:

Electronics Letters  (Volume:30 ,  Issue: 13 )