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AT2-optimal Galois field multiplier for VLSI

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2 Author(s)
M. Furer ; Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA ; K. Mehlhorn

VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT2-optimal Galois-field multiplier based on AT 2-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials (of degree n-1) over Zp are multiplied, and then the resulting polynomial is reduced modulo a fixed irreducible polynomial (of degree n). Multiplication of polynomials is done by discrete Fourier transform (DFT). For p=2, the procedure is more involved for Z p[x] than for Z[x]. An extension to the case of variable p is included and some open problems are stated

Published in:

IEEE Transactions on Computers  (Volume:38 ,  Issue: 9 )