An incremental algorithm for computation of sums of squares is presented that is suitable for both most-significant-bit- (MSB-)first and least-significant-bit- (LSB-)first bit-sequential operation. By exploiting symmetry properties of numerical values and evaluation times in the bit-product matrix, it is shown how incremental multipliers can be converted to perform squaring at reduced hardware cost, and sum of squaring at a hardware cost to that of scalar multiplication. By the elimination of redundant computation, existing hardware modules are either reduced in size or assigned to the evaluation of a second squaring computation. The corresponding hardware architectures are derived from a simple conversion of existing incremental scalar multipliers. This conversion process is less practical on standard serial/parallel or serial-pipeline multipliers. A digit-on-line algorithm is outlined for magnitude extraction operations on plane vectors.<>
Published in:
Computers, IEEE Transactions on
(Volume:38
,
Issue:
9
)
Date of Publication:
Sept. 1989
- Page(s):
-
1325
-
1328
- ISSN :
-
0018-9340
- INSPEC Accession Number:
-
3488968
- Digital Object Identifier :
-
10.1109/12.29472
- Product Type:
-
Journals & Magazines
- Date of Current Version :
-
27 September 2004
- Issue Date :
-
Sept. 1989
- Sponsored by :
-
IEEE Computer Society