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The role of long and short paths in circuit performance optimization

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4 Author(s)
Siu Wing Cheng ; Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA ; Hsi-Chuan Chen ; D. H. C. Du ; A. Lim

In this paper, we consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between the longest path delay and the shortest path delay. The other two take the functionality of the circuit into consideration and, therefore, are usually smaller than the first one. To bring in the functionality of the circuit, we make use of a new class of paths-called the shortest destabilizing paths-as well as the longest sensitizable paths. We also show that considering both the longest sensitizable path and the shortest destabilizing path together does not always give a valid bound. The bounds on the clock period can be alternatively viewed as optimization objectives. At the physical level, the complexity of optimization very much depends on the number of long and short paths present and the number of gates shared by them. We conducted preliminary experiments to study this

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:13 ,  Issue: 7 )