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Bit-level systolic array for fast exponentiation in GF(2m)

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1 Author(s)
Chin-Liang Wang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2m). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2m) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design

Published in:

IEEE Transactions on Computers  (Volume:43 ,  Issue: 7 )