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New advances in path delay fault testing of combinational circuits

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2 Author(s)
Xiaodong Xie ; Dept. of Electr. Eng., Rochester Univ., NY, USA ; Albicki, A.

We show that not all path delay faults in a prime and irredundant two-level circuit need to be tested by robust tests in order to avoid test invalidation. This finding leads to a simplified testing procedure which guarantees 100% path delay fault testability. For the collapsible multi-level circuits, we introduce the concepts of m-primeness and m-irredundancy similar to the concepts used in two-level circuits. We prove that all path delay faults in a m-prime and m-irredundant multi-level circuit are virtually testable without testing invalidation. For the uncollapsible multi-level circuits, we propose a novel modular-based path delay fault model. Using this new model, the number of target path delay faults is substantially reduced

Published in:

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Date of Conference:

25-28 Apr 1994

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