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Realization of fully path-delay-fault testable non-scan sequential circuits

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2 Author(s)
Ke, W. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Menon, P.R.

We present a new approach to synthesizing fully path-delay-fault testable non-scan sequential circuits. Two methods are proposed. Given the state transition graph of a finite state machine, one of our methods generates a fully robustly testable circuit while the other method, which may lead to more area-efficient circuits, guarantees robust or validatable non-robust tests for all paths

Published in:

VLSI Test Symposium, 1994. Proceedings., 12th IEEE

Date of Conference:

25-28 Apr 1994