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Clock-feedthrough compensated sample/hold circuits

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2 Author(s)
K. Watanabe ; Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan ; S. Ogawa

A novel circuit technique is presented to eliminate the clock feedthrough effect in a sample/hold circuit. The device requirement is minimal, and thus it is quite useful for CMOS monolithic implementation of precise sampled analogue signal processing circuits. Experimental waveforms are also given to demonstrate its validity.<>

Published in:

Electronics Letters  (Volume:24 ,  Issue: 19 )