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The design for a Josephson micro-pipelined processor

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4 Author(s)
Y. Harada ; Dept. of Electr. Eng., Kokushikan Univ., Japan ; W. Hioe ; K. Takagi ; U. Kawabe

A novel processor with micro-pipelined architecture is proposed for latch-type Josephson logic devices. The processor is segmented into several operating stages activated by a multi-phase power system. Independent register groups are allocated to each stage in order to support pipeline processing of several instruction streams. This architecture allows building of a fine pipeline pitch processor which is capable of MIMD processing. A 12-bit micro-pipelined Josephson processor, containing an ALU, a multiplier and 16 registers, is described. Driven by a 3-phase AC power system, it is able to process 4 instruction streams simultaneously. A pipeline pitch of 3.3 GHz is expected using conventional Josephson device technology. A 4-bit processor design for 12-bit data length is also discussed.<>

Published in:

IEEE Transactions on Applied Superconductivity  (Volume:4 ,  Issue: 2 )